PowerLattice Secures Investment from Former Intel CEO Pat Gelsinger

The Growing Demand for Energy Efficiency in AI Computing

Leading technology corporations are consistently highlighting a critical challenge: a shortage of computing resources to meet the escalating demands of artificial intelligence. This signifies that the large language models powering current AI applications require an increased number of data centers for both training and inference processes, consequently demanding more electrical power.

Consequently, energy efficiency has rapidly become a paramount concern for semiconductor manufacturers.

PowerLattice: A Novel Approach to Power Delivery

Founded in 2023 by experienced electrical engineers formerly of Qualcomm, NUVIA, and Intel, PowerLattice asserts the development of a revolutionary technology capable of reducing the power consumption of computer chips by over 50%.

The startup recently concluded its stealth phase, announcing a $25 million Series A funding round spearheaded by Playground Global and Celesta Capital, bringing the total funding secured to $31 million.

Industry Validation and Expertise

“The core challenge lies in efficiently delivering power to the device itself. There are remarkably few teams and individuals possessing the necessary expertise,” stated Pat Gelsinger, general partner at Playground Global.

“We’ve assembled what I consider to be the leading team in power delivery technology.”

Gelsinger’s prior role as CEO of Intel lends substantial weight to his assessment, providing a significant endorsement of PowerLattice’s capabilities.

During a pitch meeting in March, Dr. Peng Zou, PowerLattice’s CEO, and the founding team were reportedly awestruck by Gelsinger’s presence, even requesting a photograph with him, as shared with TechCrunch.

This admiration was reciprocated, with Gelsinger expressing genuine enthusiasm for PowerLattice’s technological innovation.

The Technology Behind the Efficiency

The startup’s technology centers around a compact power delivery chiplet designed to position power sources closer to the processor.

This proximity significantly minimizes energy loss during transmission.

Production and Future Testing

After two years of development, PowerLattice has reached a key milestone: the initial production of its chiplets is underway through TSMC.

An unnamed manufacturer is currently evaluating the functionality of these chiplets, according to Gelsinger.

The startup intends to offer its product for testing by additional customers starting in the first half of 2026.

These trials will be crucial, considering PowerLattice’s potential clientele includes major chipmakers like Nvidia, Broadcom, and AMD, alongside specialized AI chip developers such as Cerberus, Grok, d-Matrix, and NextSilicon.

Market Potential and Competition

While established chip companies maintain internal teams focused on enhancing energy efficiency, Gelsinger anticipates that PowerLattice’s innovative solution will attract considerable interest.

“Companies may choose to allocate some production volume to our approach while continuing with their traditional methods,” he explained.

“However, we are confident in our ability to rapidly gain a substantial market share.”

PowerLattice is not alone in addressing the energy challenges faced by chip manufacturers.

A primary competitor is Empower Semiconductor, which secured a $140 million Series D funding round led by Fidelity Management & Research Company in September.

Looking Ahead

Gelsinger firmly believes that PowerLattice’s 50% energy efficiency improvement represents an “extraordinary” achievement.

He anticipates the company will soon secure a significantly larger funding round to support full-scale production.

“The concept is ambitious, the potential benefits are substantial, and we expect to see others pursuing similar solutions,” Gelsinger concluded.