edgeq reveals more details behind its next-gen 5g/ai chip

The current advancement in wireless technology is 5G, and numerous established and emerging companies are vying for a position in this highly competitive, yet remarkably profitable, market. A particularly noteworthy new entrant is EdgeQ, a startup distinguished by its strong technical foundation stemming from Qualcomm, which we previously highlighted following its successful $40 million Series A funding round last year.

Until recently, the company maintained a low profile regarding its technological developments while finalizing its design (its website previously displayed a standard WordPress placeholder). However, today marks the first time EdgeQ has disclosed more comprehensive details (and simultaneously updated its online presence).

A key aspect of its system-on-a-chip (SoC) architecture is its foundation on RISC-V. In contrast to processor designs like x86 and Arm, RISC-V is an open-source standard, and represents one of the earliest open architectures to achieve significant adoption and a thriving ecosystem. This has spurred the creation of numerous new companies building upon it, including EdgeQ and SiFive, which we examined late last year.

Vinay Ravuri, EdgeQ’s founder and CEO, explained that utilizing RISC-V enables EdgeQ to deliver chips that combine the adaptability of reprogrammable processors, such as FPGAs, with a more streamlined and integrated product offering improved power efficiency. He believes this addresses a significant challenge in the current 5G rollout within the wireless communications sector.

“In a closed system, components integrate efficiently and perform predictably,” he stated, referencing industry leaders like Huawei and Ericsson whose integrated base stations are widely used globally. However, customers can feel restricted by reliance on a single, non-replaceable supplier. Conversely, a completely open system based on standards like OpenRAN often results in “a less refined solution” assembled from disparate components. This can lead to higher power consumption as the parts were not originally engineered for seamless interoperability.

Ravuri asserts that EdgeQ occupies a middle ground, providing an expandable system that is also fully integrated and potentially reduces power consumption for a wireless base station by as much as 50%. The core of this lies in integrating machine learning into wireless communications through a superior SoC and ensuring all components function in harmony. “The true value of these communications chips resides in the algorithms,” he said. “We’re not simply selling silicon or connecting logic gates; we’re delivering an algorithm for the physical layer of communications.”

Adil Kidwai, VP and head of product at EdgeQ, explained that “At its core, the system utilizes hardware instructions governed by software… It’s a ‘soft’ modem characterized by exceptionally low power usage.” Because EdgeQ is built on RISC-V, the existing toolchain within that ecosystem is also applicable to the company’s product, allowing engineers to leverage compilers and debuggers already developed for RISC-V. Ravuri added that EdgeQ has incorporated approximately 50 to 100 custom vector extensions to the foundational RISC-V implementation to enhance performance.

Now that the product design is more solidified, the company plans to begin providing samples to customers in the first half of this year. “Following the sampling phase, customers will undergo a productization process,” he said, with the expectation of initiating revenue growth by 2022. The EdgeQ base station is designed to be compatible with OpenRAN option 7.x and option 6, according to the company.

The company also announced today that Paul Jacobs, the former CEO of Qualcomm, and Matt Grob, the company’s former CTO, have officially joined EdgeQ’s advisory board. Both individuals initially connected with Ravuri during his time at Qualcomm and have remained engaged with EdgeQ’s progress.